/*
 * Copyright 2018 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/soc.h>

#include "board_common.h"

void setup_iomux_i2c(void)
{
	/* I2C0 - Serial Data Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C0_SDA,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PB_00));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C0_SDA,
	       SIUL2_IMCRn(SIUL2_PB_00_IMCR_S32V_I2C0_SDA));

	/* I2C0 - Serial Clock Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C0_SCLK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PB_01));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C0_SCLK,
	       SIUL2_IMCRn(SIUL2_PB_01_IMCR_S32V_I2C0_SCLK));

	/* I2C1 - Serial Data Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C1_SDA,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PA_06));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C1_SDA,
	       SIUL2_IMCRn(SIUL2_PA_06_IMCR_S32V_I2C1_SDA));

	/* I2C1 - Serial Clock Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C1_SCLK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PA_07));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C1_SCLK,
	       SIUL2_IMCRn(SIUL2_PA_07_IMCR_S32V_I2C1_SCLK));

	/* I2C2 - Serial Data Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C2_SDA,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PA_14));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C2_SDA,
	       SIUL2_IMCRn(SIUL2_PA_14_IMCR_S32V_I2C2_SDA));

	/* I2C2 - Serial Clock Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C2_SCLK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PA_15));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C2_SCLK,
	       SIUL2_IMCRn(SIUL2_PA_15_IMCR_S32V_I2C2_SCLK));

	/* I2C3 - Serial Data Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C3_SDA,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PB_06));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C3_SDA,
	       SIUL2_IMCRn(SIUL2_PB_06_IMCR_S32V_I2C3_SDA));

	/* I2C3 - Serial Clock Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C3_SCLK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PB_07));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C3_SCLK,
	       SIUL2_IMCRn(SIUL2_PB_07_IMCR_S32V_I2C3_SCLK));

	/* I2C4 - Serial Data Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C4_SDA,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PD_11));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C4_SDA,
	       SIUL2_IMCRn(SIUL2_PD_11_IMCR_S32V_I2C4_SDA));

	/* I2C4 - Serial Clock Input */
	writel(SIUL2_MSCR_S32V_PAD_CTRL_I2C4_SCLK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PC_13));
	writel(SIUL2_IMCR_S32V_PAD_CTRL_I2C4_SCLK,
	       SIUL2_IMCRn(SIUL2_PC_13_IMCR_S32V_I2C4_SCLK));
}

#ifdef CONFIG_FSL_DSPI
static void setup_iomux_dspi(void)
{
	/* Configure Chip Select Pins */
	/* RGMII_C_SPI_CS SJA1105  */
	writel(SUIL2_MSCR_S32V_PAD_CTL_SPI0_CS0,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PJ_09));
	/* PMIC PF8530 CS */
	writel(SUIL2_MSCR_S32V_PAD_CTL_SPI0_CS1,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PJ_10));

	/* MSCR */
	writel(SIUL2_MSCR_S32V_PAD_CTL_SPI0_SOUT,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PJ_08));

	writel(SIUL2_MSCR_S32V_PAD_CTL_SPI0_SIN,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PJ_07));

	writel(SIUL2_MSCR_S32V_PAD_CTL_SPI0_SCK,
	       SIUL2_MSCRn(SIUL2_MSCR_S32V_PJ_06));

	/* IMCR */
	writel(SIUL2_IMCR_S32V_PAD_CTL_SPI0_SIN,
	       SIUL2_IMCRn(SIUL2_PJ_07_IMCR_S32V_SPI0_SIN));
}
#endif
